Accounts for delays outside the current module.
Before starting DC, you must set up the environment correctly. The configuration is largely controlled by a file named .synopsys_dc.setup in your working directory. This hidden file tells DC where to find all the necessary design data and libraries. The key libraries you need to define are:
Let’s walk through a practical session using a simple 32-bit RISC-V processor (e.g., rv32i_core.v ). We’ll target a library (simulated in the tutorial).
The standard cell library (.db) used for mapping logic.
# Setup Variables set link_library "* standard_cell_lib.db" set target_library "standard_cell_lib.db" set symbol_library "standard_cell_lib.sdb" set search_path ". /path/to/libraries /path/to/rtl" Use code with caution.
Synopsys: Design Compiler Tutorial 2021
Accounts for delays outside the current module.
Before starting DC, you must set up the environment correctly. The configuration is largely controlled by a file named .synopsys_dc.setup in your working directory. This hidden file tells DC where to find all the necessary design data and libraries. The key libraries you need to define are: synopsys design compiler tutorial 2021
Let’s walk through a practical session using a simple 32-bit RISC-V processor (e.g., rv32i_core.v ). We’ll target a library (simulated in the tutorial). Accounts for delays outside the current module
The standard cell library (.db) used for mapping logic. synopsys design compiler tutorial 2021
# Setup Variables set link_library "* standard_cell_lib.db" set target_library "standard_cell_lib.db" set symbol_library "standard_cell_lib.sdb" set search_path ". /path/to/libraries /path/to/rtl" Use code with caution.